1. Field of the Invention
This invention relates to the field of microprocessors and, more particularly, to the control of pipelines within microprocessors.
2. Description of the Related Art
Superscalar microprocessors achieve high performance by executing multiple instructions per clock cycle and by choosing the shortest possible clock cycle consistent with the design. As used herein, the term "clock cycle" refers to an interval of time accorded to various stages of an instruction processing pipeline within the microprocessor. Storage devices (e.g. registers and arrays) capture their values according to the clock cycle. For example, a storage device may capture a value according to a rising or falling edge of a clock signal defining the clock cycle. The storage device then stores the value until the subsequent rising or falling edge of the clock signal, respectively. The term "instruction processing pipeline" is used herein to refer to the logic circuits employed to process instructions in a pipelined fashion.
Generally speaking, a pipeline comprises a number of pipeline stages at which portions of a particular task are performed. The portion of the particular task performed at a given pipeline stage comprises the "operation" performed by that pipeline stage. Different stages may simultaneously operate upon different items, thereby increasing overall throughput. Although the instruction processing pipeline may be divided into any number of pipeline stages at which operations comprising instruction processing are performed, instruction processing generally comprises fetching the instruction, decoding the instruction, executing the instruction, and storing the execution results in the destination identified by the instruction.
Instruction processing pipelines may be quite complex. Particularly, different instructions may follow different paths through the instruction processing pipeline. For example, an instruction may not require the operation performed by a particular pipeline stage. Therefore, the instruction may skip the particular pipeline stage and be conveyed directly from a pipeline stage preceding the particular pipeline stage to the pipeline stage succeeding the particular pipeline stage in the instruction processing pipeline. Still further, a particular pipeline stage may provide an instruction to one of a number of pipeline stages depending upon the instruction. For example, floating point instructions often perform either a multiplication operation or an addition operation. Therefore, a particular floating point instruction may be routed to a pipeline stage or stages for performing addition or another set of pipeline stage or stages for performing multiplication. Similarly, integer instructions may be routed to different pipeline stages based upon the definition of the instruction.
Each pipeline stage of the instruction processing pipeline incorporates dataflow elements for performing the operation defined for that stage. The dataflow elements often require control signals to direct the operation of the dataflow elements upon input operands in order to produce a result. The control signals may vary according to the instruction conveyed to the pipeline stage. For example, an adder dataflow element may require a carry-in input which is to be added to the operand values being added. Certain instructions may define the carry-in to be zero, while others may define the carry-in to be a condition flag defined by the microprocessor architecture. Therefore, the carry-in control signal for the adder dataflow element is generated by the stage according to the instruction.
Typically, such routing of instructions to one of a set of pipeline stages and the control of dataflow elements in a particular pipeline stage is performed via specialized decode logic within each pipeline stage. The pipeline stage determines how to route the instruction and the control signals dictated by the instruction from the instruction information provided to the stage (e.g. opcode, addressing modes used by the instruction, etc.). Unfortunately, if the pipeline is modified by adding or deleting pipeline stages or by redefining the operation performed at a given pipeline stage, the decode logic incorporated into many of the pipeline stages may require modification. Locating and correctly modifying the decode logic is a difficult and time consuming task. A better method for performing control within pipeline stages and routing between pipeline stages is therefore desired.